An integrated circuit (IC) is a set of electronic circuits that integrates a large number of semiconducting transistors into a small chip. Among the most advanced integrated circuits are microprocessors, memory chips, programmable logic sensors, power management circuits, etc. Advances in IC technology have led to size reduction of transistors, enabling greater densities of devices and circuits in IC chips and enhanced performance.
The fabrication of an IC chip involves a lengthy and detailed series of exacting process steps, including such steps as lithography, doping, etching, chemical mechanical polishing, and the like. Manufacturers are constantly updating their processes or developing new ones, and it is rarely obvious how a small change in the recipe will affect the performance of integrated circuits made using the new recipe. Usually, test structures are fabricated using the new process, and these structures are evaluated by observing their features and performance. Process engineers then revise the recipe further and try again. But fabrication can be costly and time-consuming, and thus cannot be performed as often during process development as would be desired. Some aspects of the evaluation can be performed by simulation, in a technique sometimes referred to herein as Design Technology Co-Optimization (DTCO). However, many needed aspects of the evaluation still require physical fabrication of test structures.
All circuit elements in a library cell such as interconnect, diodes, and transistors have internal parasitic capacitance and resistance, which can cause their behavior to depart from that of ‘ideal’ circuit elements. As transistors are scaled down in size, the overall parasitic capacitance in the IC increases as the space between neighboring devices decreases to tens of nanometers to pack more computing power into smaller spaces. Small contact size between source/drain and interconnects leads to higher contact resistance and contact-to-gate capacitance. Therefore the parasitic effect is an important metric in the evaluation of future transistor and electronic devices.
A goal of DTCO is to obtain a power-performance-area evaluation of a circuit design, based on the layout of the circuit design and a description of the process flow under test, early in the development of the fabrication process, before physical test structures are readily available. The evaluation still involves a SPICE model of the transistors in the cell, but typically this model is extracted only for a nominal transistor. It does not account for parasitic resistance and capacitance of interconnects in the layout, which can contribute large variations in the performance of the circuit. The values for the parasitic resistance and capacitance in the SPICE model for the nominal transistor can differ significantly from actual parasitic resistance and capacitance. Such differences can arise because each interconnect in the circuit design has different surroundings, physical locations in the circuit design layout, loads, fan-in, and so on. For timing analysis of the library cell, it is important that timing delays and parasitic resistances and capacitances associated with the circuit components in the netlist be accurate.